The present invention relates to a semiconductor device and can be used appropriately for a semiconductor device in which a plurality of semiconductor components such as, e.g., semiconductor chips are electrically coupled to each other via an interposer.
Japanese Unexamined Patent Publication No. 2012-238804 (Patent Document 1) describes a printed wiring board in which an IC chip is embedded in a first resin insulating layer, a second resin insulating layer is formed over the first resin insulating layer, and a second conductor layer thicker than a third conductor layer is disposed at the interface between the first and second resin insulating layers.
On the other hand, Japanese Unexamined Patent Publication No. 2001-016007 (Patent Document 2) describes a wiring substrate formed with a transmission line including a strip line, a dielectric layer formed so as to surround the strip line, two ground lines between which the dielectric layer is interposed in a vertical direction, and two elongated-hole-shaped via conductors which conductively couple the two ground lines to each other and between which the dielectric layer is interposed in a lateral direction.